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+From cd01b277c4a9e03c83427290228e4b289a169431 Mon Sep 17 00:00:00 2001
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+From: Gopi Kumar Bulusu <gopi@sankhya.com>
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+Date: Thu, 10 Jul 2025 12:44:44 +0530
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+Subject: [PATCH] MicroBlaze : Enhance support for atomics. Fix PR118280
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+
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+Atomic support enhanced to fix existing atomic_compare_and_swapsi pattern
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+to handle side effects; new patterns atomic_fetch_op and atomic_test_and_set
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+added. As MicroBlaze has no QImode test/set instruction, use shift magic
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+to implement atomic_test_and_set. This fixes PR118280.
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+
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+Files Changed
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+
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+* gcc/config/microblaze/iterators.md: New
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+* microblaze-protos.h/microblaze.cc : Add microblaze_subword_address
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+* gcc/config/microblaze/microblaze.md: constants: Add UNSPECV_CAS_BOOL,
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+ UNSPECV_CAS_MEM, UNSPECV_CAS_VAL, UNSPECV_ATOMIC_FETCH_OP
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+ type: add atomic
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+* gcc/config/microblaze/sync.md: Add atomic_fetch_<atomic_optab>si
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+ atomic_test_and_set
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+
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+Fixes: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118280
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+Upstream: https://patchwork.ozlabs.org/project/gcc/list/?series=466193
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+
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+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
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+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
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+Signed-off-by: Gopi Kumar Bulusu <gopi@sankhya.com>
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+---
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+ gcc/config/microblaze/iterators.md | 25 +++++
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+ gcc/config/microblaze/microblaze-protos.h | 1 +
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+ gcc/config/microblaze/microblaze.cc | 28 ++++++
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+ gcc/config/microblaze/microblaze.h | 2 +-
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+ gcc/config/microblaze/microblaze.md | 7 +-
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+ gcc/config/microblaze/sync.md | 107 ++++++++++++++++++----
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+ 6 files changed, 150 insertions(+), 20 deletions(-)
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+ create mode 100644 gcc/config/microblaze/iterators.md
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+
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+diff --git a/gcc/config/microblaze/iterators.md b/gcc/config/microblaze/iterators.md
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+new file mode 100644
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+index 00000000000..2ffc2422a0a
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+--- /dev/null
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++++ b/gcc/config/microblaze/iterators.md
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+@@ -0,0 +1,25 @@
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++;; Iterator definitions for GCC MicroBlaze machine description files.
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++;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
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++;;
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++;; This file is part of GCC.
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++;;
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++;; GCC is free software; you can redistribute it and/or modify
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++;; it under the terms of the GNU General Public License as published by
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++;; the Free Software Foundation; either version 3, or (at your option)
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++;; any later version.
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++;;
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++;; GCC is distributed in the hope that it will be useful,
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++;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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++;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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++;; GNU General Public License for more details.
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++;;
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++;; You should have received a copy of the GNU General Public License
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++;; along with GCC; see the file COPYING3. If not see
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++;; <http://www.gnu.org/licenses/>.
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++
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++; atomics code iterator
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++(define_code_iterator any_atomic [plus ior xor and])
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++
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++; atomics code attribute
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++(define_code_attr atomic_optab
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++ [(plus "add") (ior "or") (xor "xor") (and "and")])
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+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
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+index 90b79cfe716..1cee0b3096c 100644
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+--- a/gcc/config/microblaze/microblaze-protos.h
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++++ b/gcc/config/microblaze/microblaze-protos.h
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+@@ -62,6 +62,7 @@ extern int symbol_mentioned_p (rtx);
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+ extern int label_mentioned_p (rtx);
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+ extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
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+ extern void microblaze_eh_return (rtx op0);
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++extern void microblaze_subword_address (rtx, rtx *, rtx *);
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+ #endif /* RTX_CODE */
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+
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+ /* Declare functions in microblaze-c.cc. */
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+diff --git a/gcc/config/microblaze/microblaze.cc b/gcc/config/microblaze/microblaze.cc
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+index 2ab5ada4ec9..80d10ab60e0 100644
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+--- a/gcc/config/microblaze/microblaze.cc
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++++ b/gcc/config/microblaze/microblaze.cc
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+@@ -1299,6 +1299,34 @@ microblaze_expand_block_move (rtx dest, rtx src, rtx length, rtx align_rtx)
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+ return false;
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+ }
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+
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++/* Compute memory address *aligned_mem and corresponding shift value (*shift)
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++ from a QImode memory reference MEM */
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++void
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++microblaze_subword_address (rtx mem, rtx *aligned_mem, rtx *shift)
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++{
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++ /* Align the memory address to a word. */
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++ rtx addr = force_reg (Pmode, XEXP (mem, 0));
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++
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++ rtx addr_mask = gen_int_mode (-4, Pmode);
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++
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++ rtx aligned_addr = gen_reg_rtx (Pmode);
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++
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++ emit_move_insn (aligned_addr, gen_rtx_AND (Pmode, addr, addr_mask));
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++
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++ *aligned_mem = change_address (mem, SImode, aligned_addr);
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++
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++ /* Calculate the shift amount. */
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++ emit_move_insn (*shift, gen_rtx_AND (SImode, addr, gen_int_mode (3, SImode)));
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++
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++ if (TARGET_LITTLE_ENDIAN == 0) {
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++ emit_move_insn (*shift,
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++ gen_rtx_MINUS (SImode, gen_int_mode (3, SImode), *shift));
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++ }
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++
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++ emit_move_insn (*shift, gen_rtx_ASHIFT (SImode, *shift,
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++ gen_int_mode (3, SImode)));
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++}
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++
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+ static bool
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+ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
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+ int opno ATTRIBUTE_UNUSED, int *total,
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+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
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+index 2390542434b..b2e9ccde363 100644
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+--- a/gcc/config/microblaze/microblaze.h
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++++ b/gcc/config/microblaze/microblaze.h
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+@@ -57,7 +57,7 @@ extern enum pipeline_type microblaze_pipe;
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+
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+ /* Default target_flags if no switches are specified */
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+ #define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT \
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+- | TARGET_ENDIAN_DEFAULT)
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++ | TARGET_ENDIAN_DEFAULT)
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+
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+ /* Do we have CLZ? */
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+ #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
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+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
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+index 45c48a71e8d..270df8da0c5 100644
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+--- a/gcc/config/microblaze/microblaze.md
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++++ b/gcc/config/microblaze/microblaze.md
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+@@ -21,6 +21,7 @@
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+
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+ (include "constraints.md")
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+ (include "predicates.md")
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++(include "iterators.md")
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+
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+ ;;----------------------------------------------------
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+ ;; Constants
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+@@ -43,6 +44,10 @@
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+ (UNSPEC_TLS 106) ;; jump table
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+ (UNSPEC_SET_TEXT 107) ;; set text start
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+ (UNSPEC_TEXT 108) ;; data text relative
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++ (UNSPECV_CAS_BOOL 201) ;; compare and swap (bool)
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++ (UNSPECV_CAS_VAL 202) ;; compare and swap (val)
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++ (UNSPECV_CAS_MEM 203) ;; compare and swap (mem)
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++ (UNSPECV_ATOMIC_FETCH_OP 204) ;; atomic fetch op
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+ ])
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+
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+ (define_c_enum "unspec" [
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+@@ -79,7 +84,7 @@
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+ ;; bshift Shift operations
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+
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+ (define_attr "type"
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+- "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
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++ "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap,atomic"
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+ (const_string "unknown"))
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+
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+ ;; Main data type used by the insn
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+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
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+index db7b11e5379..6478ab6dcac 100644
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+--- a/gcc/config/microblaze/sync.md
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++++ b/gcc/config/microblaze/sync.md
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+@@ -18,26 +18,97 @@
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+ ;; <http://www.gnu.org/licenses/>.
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+
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+ (define_insn "atomic_compare_and_swapsi"
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+- [(match_operand:SI 0 "register_operand" "=&d") ;; bool output
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+- (match_operand:SI 1 "register_operand" "=&d") ;; val output
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+- (match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
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+- (match_operand:SI 3 "register_operand" "d") ;; expected value
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+- (match_operand:SI 4 "register_operand" "d") ;; desired value
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+- (match_operand:SI 5 "const_int_operand" "") ;; is_weak
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+- (match_operand:SI 6 "const_int_operand" "") ;; mod_s
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+- (match_operand:SI 7 "const_int_operand" "") ;; mod_f
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++ [(set (match_operand:SI 0 "register_operand" "=&d") ;; bool output
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++ (unspec_volatile:SI
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++ [(match_operand:SI 2 "nonimmediate_operand" "+Q") ;; memory
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++ (match_operand:SI 3 "register_operand" "d") ;; expected value
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++ (match_operand:SI 4 "register_operand" "d")] ;; desired value
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++ UNSPECV_CAS_BOOL))
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++ (set (match_operand:SI 1 "register_operand" "=&d") ;; val output
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++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
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++ (set (match_dup 2)
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++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
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++ (match_operand:SI 5 "const_int_operand" "") ;; is_weak
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++ (match_operand:SI 6 "const_int_operand" "") ;; mod_s
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++ (match_operand:SI 7 "const_int_operand" "") ;; mod_f
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+ (clobber (match_scratch:SI 8 "=&d"))]
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+ ""
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+ {
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+- output_asm_insn ("addc \tr0,r0,r0", operands);
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+- output_asm_insn ("lwx \t%1,%y2,r0", operands);
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+- output_asm_insn ("addic\t%8,r0,0", operands);
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+- output_asm_insn ("bnei \t%8,.-8", operands);
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+- output_asm_insn ("cmp \t%0,%1,%3", operands);
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+- output_asm_insn ("bnei \t%0,.+16", operands);
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+- output_asm_insn ("swx \t%4,%y2,r0", operands);
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+- output_asm_insn ("addic\t%8,r0,0", operands);
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+- output_asm_insn ("bnei \t%8,.-28", operands);
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+- return "";
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++ return "add \t%0,r0,r0\n\t"
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++ "lwx \t%1,%y2,r0\n\t"
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++ "addic\t%8,r0,0\n\t"
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++ "bnei \t%8,.-8\n\t"
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++ "cmp \t%8,%1,%3\n\t"
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++ "bnei \t%8,.+20\n\t"
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++ "swx \t%4,%y2,r0\n\t"
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++ "addic\t%8,r0,0\n\t"
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++ "bnei \t%8,.-28\n\t"
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++ "addi \t%0,r0,1";
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+ }
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++ [(set_attr "type" "atomic")
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++ (set_attr "mode" "SI")
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++ (set_attr "length" "40")]
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+ )
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++
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++;;
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++;;
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++;;
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++;;
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++(define_insn "atomic_fetch_<atomic_optab>si"
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++ [(set (match_operand:SI 0 "register_operand" "=&d")
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++ (match_operand:SI 1 "memory_operand" "+Q"))
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++ (set (match_dup 1)
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++ (unspec_volatile:SI
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++ [(any_atomic:SI (match_dup 1)
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++ (match_operand:SI 2 "register_operand" "d"))
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++ (match_operand:SI 3 "const_int_operand")] ;; model
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++ UNSPECV_ATOMIC_FETCH_OP))
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++ (clobber (match_scratch:SI 4 "=&d"))] ;; tmp_1
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++ ""
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++ {
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++ return
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++ "lwx \t%0,%y1,r0\n\t"
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++ "addic\t%4,r0,0\n\t"
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++ "bnei \t%4,.-8\n\t"
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++ "<atomic_optab>\t%4,%0,%2\n\t"
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++ "swx \t%4,%y1,r0\n\t"
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++ "addic\t%4,r0,0\n\t"
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++ "bnei \t%4,.-24";
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++ }
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++ [(set_attr "type" "atomic")
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++ (set_attr "mode" "SI")
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++ (set_attr "length" "28")])
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++
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++;;
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++;; MicroBlaze only supports lx/sx instructions for word mode only
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++;;
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++;; Use shift|mask magic to implement atomic_test_and_set using lwx/swx
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++;;
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++(define_expand "atomic_test_and_set"
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++ [(match_operand:QI 0 "register_operand" "") ;; bool output
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++ (match_operand:QI 1 "memory_operand" "m") ;; memory
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++ (match_operand:SI 2 "const_int_operand" "")] ;; model
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++ ""
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++{
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++ rtx old = gen_reg_rtx (SImode);
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++ rtx mem = operands[1];
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++ rtx model = operands[2];
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++ rtx set = gen_reg_rtx (SImode);
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++ rtx aligned_mem = gen_reg_rtx (SImode);
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++ rtx shift = gen_reg_rtx (SImode);
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++
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++ microblaze_subword_address (mem, &aligned_mem, &shift);
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++
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++ emit_move_insn (set, GEN_INT (1));
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++ rtx shifted_set = gen_reg_rtx (SImode);
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++
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++ emit_move_insn (shifted_set, gen_rtx_ASHIFT (SImode, set, shift));
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++
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++ emit_insn (gen_atomic_fetch_orsi (old, aligned_mem, shifted_set, model));
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++
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++ emit_move_insn (old, gen_rtx_ASHIFTRT (SImode, old, shift));
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++
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++ emit_move_insn (operands[0], gen_lowpart (QImode, old));
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++
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++ DONE;
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++})
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+--
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+2.43.5
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+
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Neal Frager